Project:RISC-V

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RISC-V project
Description RISC-V architecture support project
Project email riscv@gentoo.org
IRC channel #gentoo-riscv
Lead(s) none
No lead election date set
Member(s)
Subproject(s)
(and inherited member(s))
(none)
Parent Project Gentoo Base System
Project listing

The RISC-V project is an effort to bring first-class RISC-V CPU architecture support in Gentoo.

Status

No first class arch support yet. Early adopters can get a toolchain working.

What works

With help of crossdev and a bit of manual '*'/'~*' keywording you can get the following toolchains to work:

  • riscv64-unknown-linux-gnu: linux glibc target to cross-compile your kernel and stage3 userland
  • riscv64-unknown-elf: newlib target (bare metal?)

qemu-riscv can run the binaries just fine: qemu-riscv64 -L /usr/riscv64-unknown-linux-gnu/ /usr/riscv64-unknown-linux-gnu/bin/bash

What needs to be done

Things to happen yet:

Documentation

  • TODO: Add a page that describes how to get riscv toolchain. Basically a crossdev -t riscv64-unknown-linux-gnu and a few tweaks around.
  • TODO: Describe arch-specific gotchas (alignment requirements, immediate encodings, PIS crosry).
  • TODO: Add external links to ISA and ABI docs.
  • RISC-V ABIs
  • RISC-V Multilib