|Description||RISC-V architecture support project|
|Lead(s)|| none |
No lead election date set
(and inherited member(s))
|Parent Project||Gentoo Base System|
The RISC-V project is an effort to bring first-class RISC-V CPU architecture support in Gentoo.
No first class arch support yet. Early adopters can get a toolchain working.
With help of crossdev and a bit of manual '*'/'~*' keywording you can get the following toolchains to work:
- riscv64-unknown-linux-gnu: linux glibc target to cross-compile your kernel and stage3 userland
- riscv64-unknown-elf: newlib target (bare metal?)
qemu-riscv can run the binaries just fine: qemu-riscv64 -L /usr/riscv64-unknown-linux-gnu/ /usr/riscv64-unknown-linux-gnu/bin/bash
What needs to be done
Things to happen yet:
- TODO: Announce RISC-V project.
- Prepare profiles/ entries. See the overlay for a first attempt including multilib.
- TODO: Add minimal
- TODO: Make stage3 autobuilds.
- TODO: Add a page that describes how to get riscv toolchain. Basically a crossdev -t riscv64-unknown-linux-gnu and a few tweaks around.
- TODO: Describe arch-specific gotchas (alignment requirements, immediate encodings, PIS crosry).
- TODO: Add external links to ISA and ABI docs.
- RISC-V ABIs
- RISC-V Multilib