StarFive VisionFive 2/Hardware

Hardware components

The StarFive VisionFive 2 is a Single Board Computer (SBC) based on a StarFive JH7110 SoC (rv64gc subarch), an Imagination BXE-4-32 GPU and several other components detailed hereafter. It comes in variants of 2/4/8 GB of LPDDR4 memory. See the document VisionFive2_QSG.pdf for a full specification. This SBC supports TF/SD, eMMC, USB and NVMe storage devices, as well as having a 40-pin GPIO header and a 2-bit RGPIO boot device selector switch.

• CPU:
  • Model: SiFive JH7110 SoC running at 1.5 GHz with 5 HARTs (a HART is a CPU core abstraction, i.e. an execution context containing a full set of RISC-V architectural registers that executes its program independently from other HARTs)
  • Cores (HARTs):
    • 4× U7 64-bits RISC‑V cores (RV64GC) for general usage
    • 1x S7 64-bits RISC‑V core (RV64IMAC) for monitoring (not used?)
    • 1x S24 32-bits RISC‑V core for low power and control/configure tasks as a coprocessor in JH7110 SoC (not used?)
  • Datasheet: u74mc_core_complex_manual_21G1.pdf
• GPU:
  • Model: Imagination IMG BXE-4-32 MC1
  • Product page: https://www.imaginationtech.com/product/img-bxe-4-32-mc4
  • Currently supported in Linux at upstream level and also in MESA (OpenGL ES 3.x, OpenCL 3.0 and Vulkan 1.0)
  • Partial datasheet (covers registers only): rogue-registers-description-docs.zip
  • Work in progress! Datasheet should be published "soon" (see "Imagination Tech Publishes Open-Source PowerVR Vulkan Driver For Mesa" on Phoronix)
• RAM:
  • Model: BIWIN 2/4/8 GB LPDDR4
• EEPROMs:
  • Model: 24FC04H (4 kbits / 512 bytes):
    • Referred as "EEPROM" in manual
    • Stores some information like the Ethernet addresses, the product serial number, etc. No code stored here.
    • Accessed via I2C
    • Datasheet:
      • Product page: https://www.microchip.com/en-us/product/24fc04h
      • PDF document: 24AA04H-24LC04BH-24FC04H-4K-I2C-Serial-EEPROM-With-Half-Array-Write-Protect-20002119C.pdf
    • Reference mentioned in: starfive/visionfive2/visionfive2-i2c-eeprom.c (GitHub)
  • Model: GD25LQ128 (128mbit / 16 mega-bytes):
    • Referred as "QSPI Flash" or "SPI Flash" in the manual
    • Stores U-Boot and various firmware files (DTB, OpenSBI, etc).
    • Accessed via SPI
    • Datasheet:
      • Product page: https://www.gigadevice.com/product/flash/product-series/spi-nor-flash/gd25lq128d
      • PDF Document: DS-00291-GD25LQ128D-Rev1.9.pdf
• Ethernet controllers (PHY/GMAC):
  • 2x Motorcomm YT8531 (1 GbE) for board revision 1.3B (one YT8531 per Ethernet plug). Older boards use models YT8521C and YT8512C (100 MbE)
  • Datasheet: YT8531_xiliejieshaov0.3.pdf
• USB controller:
  • Model: Via Labs (VLI) VL805-Q6
  • Datasheet:
    • Description: Via Labs VL805
    • Discussion thread where the PDF datasheet is mentioned : "PCIe to 4 USB ports use vl805 chipset on jetson nano custom carrier board" (direct link)
  • Connected via the PCIe bus so shares the bandwidth
  • According to its datasheet, this controller supports USB debugging
• Power Management Integrated Controller (PMIC):
  • Model: X-Powers AXP-15060
  • Datasheet: AXP15060 datasheet V0.1.pdf

RISCV ISA standard and extensions

When identifying the RISC-V ISA standard and extensions for the target device, the following table may be useful:

Name	Description
RV32I	Base Integer Instruction Set - 32-bit
RV32E	Base Integer Instruction Set (embedded) - 32-bit, 16 registers
RV64I	Base Integer Instruction Set - 64-bit
RV128I	Base Integer Instruction Set - 128-bit
Extension
M	Standard Extension for Integer Multiplication and Division
A	Standard Extension for Atomic Instructions
F	Standard Extension for Single-Precision Floating-Point
D	Standard Extension for Double-Precision Floating-Point
G	Shorthand for the base and above extensions
Q	Standard Extension for Quad-Precision Floating-Point
L	Standard Extension for Decimal Floating-Point
C	Standard Extension for Compressed Instructions
B	Standard Extension for Bit Manipulation
J	Standard Extension for Dynamically Translated Languages
T	Standard Extension for Transactional Memory
P	Standard Extension for Packed-SIMD Instructions
V	Standard Extension for Vector Operations
N	Standard Extension for User-Level Interrupts
H	Standard Extension for Hypervisor
S	Standard Extension for Supervisor-level Instructions

RISC-V defines the order that must be used to define the ISA subset:

  RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N

For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not

In the case of the VisionFive 2, the following identifiers are both valid however the first is more descriptive: rv64imafdc, rv64gc

We have some additional extensions to take into account:

• zicsr (Control and Status Register [CSR] Instructions); implied by the F extension
• Bitmanip extensions Zba (address generation) and Zbb (Basic bit manipulation)

This results in the following being the descriptive and shorthand flags for the VisionFive2 board respectively: rv64imafdc_zicsr_zba_zbb, rv64gc_zba_zbb