Project:RISC-V

Porject:RISC-V is an effort to bring first-class RISC-V CPU architecture support in Gentoo.

= Status =

No first class arch support yet. Early adopters can get a toolchain working.

What works
With help of crossdev and a bit of manual '*'/'~*' keywording you can get the following toolchains to work:
 * riscv64-unknown-linux-gnu: linux glibc target to cross-compile your kernel and stage3 userland
 * riscv64-unknown-elf: newlib target (bare metal?)

qemu-riscv can run your binaries just fine: qemu-riscv64 -L /usr/riscv64-unknown-linux-gnu/ /usr/riscv64-unknown-linux-gnu/bin/bash

What needs to be done
Things to happen yet:


 * TODO: announce RISC-V project
 * TODO: prepare profiles/ entries
 * TODO: add minimal ~riscv keywords
 * TODO: make stage3 autobuilds
 * TODO: sort out multilib story

= Docs =

TODO: add a page that describes how to get riscv toolchain. Basically a crossdev -t riscv64-unknown-linux-gnu and a few tweaks around. TODO: describe arch-specific gochas (alignment requirements, immediate encodings, PIS crosry) TODO: add external links to ISA and ABI docs