Talk:Safe CFLAGS

The aim of this page is to create an alternative to this. Since we can not directly copy, I would suggest that users instead check their own CFLAGS and put them into this page so that we can build up a solid list of CPUs and their suggested CFLAGS.

= --march=native =

I think this page should include a chapter explaining why --march= would be better than --march=native, because it's confusing for new users to find these two different recommendations without any explanation which one is the "proper" way.
 * Although the page now mentions march=native, it still doesn't explain, why march=corei7 would be preferred (what are the benefits) over march=native, which may confuse many people. Smartass 15:54, 11 December 2012 (UTC)

I just added a section for the Core 2 Duo, and ran into a problem that touched on your comment. Apparently setting the "-march" explicitly vs using native might effect your ability to cross compile, and it may effect what processor optimizations are enabled:

Setting -march=core2 tells gcc to enable MMX, SSE, SSE2, SSE3, SSSE3 instruction set support. (Citation: http://gcc.gnu.org/onlinedocs/gcc-4.4.4/gcc/i386-and-x86_002d64-Options.html#i386-and-x86_002d64-Options  ) Setting the USE variable to include "MMX, SSE, SSE2, SSE3" would then be redundant; I believe.

Some core 2 solo/duo/quad processors support sse4, sse4a, and sse4_1. I'd like to find a safe and correct way of enabling support for sse4 sse4a, and sse4.1 in the CFLAGS and/or USE for a core 2 duo that supports them.

I don't think seting these in the USE flags is the correct way. Unless I'm mistaken, only packages that support those use flags would benefit; or am I wrong about that? Also I noticed that the sse4, sse4a, and sse4_1 USE flags are not included in the global use flag list at: http://www.gentoo.org/dyn/use-index.xml  Does there abscence from that list mean those use flags would have no effect?

One person who made a nice page about optimizing for the Core 2 solo/duo/quad (Citation: http://wiki.gentoo.org/wiki/Intel_Core_2 ) suggested just setting -march=native. GCC seems to recognize the sse4 instruction sets when I run "gcc -march=native -E -v - &1 | grep cc1" so setting -march=native might solve the problem. However sometimes I cross compile; and according to the Gentoo GCC optimization guide (  http://www.gentoo.org/doc/en/gcc-optimization.xml ) using native will cause problems when trying to cross compile. So many questions raised.... I should turn this into a forum post - It kind of got out of hand... To reiterate: I'd like to add to this page a safe and correct way of enabling support for sse4 sse4a, and sse4.1 in the CFLAGS/USE for a core 2 duo that supports them. Any one know a definitive way of identifying processor support for those processor optimizations; and how to enable them in GCC? Thank you! Aries97 (talk) 04:45, 15 May 2013 (UTC)

Update: Core2 processors support EM64T - aka AMD64. (Wikipedia: http://en.wikipedia.org/wiki/EM64T#Intel_64 ) For whatever reason; I had an i686 CHOST set earlier. I've tested this on my processor and changed the entry to reflect a corrected CHOST="x86_64-pc-linux-gnu". Aries97 (talk) 06:23, 28 May 2013 (UTC)

= Add Intel Suggested i7 Optimizations = Suggest adding Intel's suggested optimizations someplace for i7 processors. http://software.intel.com/en-us/blogs/2012/09/26/gcc-x86-performance-hints

ie. CFLAGS="-m64 -Ofast -flto -march=native -funroll-loops"

Granted this is Safe CFLAGS, and some reference should be made to the manufacturer's suggestions.

= Section Core i3/i5/i7 & Xeon E3/E5/E7 *V2 seems to be incorrect =

CFLAGS="-march=core-avx2 -O2 -pipe" is not working for my Xeon-E5 2620 which seems to be sandybridge based.

Please correct