Ryzen

Ryzen is Zen microarchitecture.]] Its goal is to directly compete with Intel's Broadwell-E processor line, primarily the Core i7-6900K.

Firmware
Microcode/firmware updates to be determined...

Kernel
Enable support for Ryzen hardware in kernel 4.11.0:

Those using with the   USE flag will have additional Processor family options made available:

This enables  to be set for the kernel's  process.

GCC 6.3+
GCC 6.3+ has support for the  compiler optimization. For optimal performance, this can be enabled in.

GCC 6.3 is not presently optimized for Ryzen.

GCC 5.4
While GCC 5.4 does not support zen core specific optimization,  has been shown to be functional and stable. However, since Zen dropped the instruction set extensions FMA4, TBM, XOP and LWP, they should be disabled accordingly:

Optional, but may produce better code: Add new instruction set extensions introduced with Zen individually (ADCX, RDSEED, MWAITX, SHA, CLZERO, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT), using  (Bulldozer Version 4 i.e. Excavator) as the starting point:

Segmentation faults during compilation
If segfaults are encountered during compilation process on Zen it might be anything from software bug to a hardware bug. There have been reports of success and failure. The recommendation is to disable all overclocking and set proper timings for RAM. These problems are likely to be fixed in the future by AMD microcode update and/or GCC update.

Please ensure the most recently compiled binutils is selected via


 * An older instance of binutils could be built against older opcode facilitating crashes due to poor linkage.
 * Ensure RAM voltage and timing are correct for the RAM; BIOSs are conservative while performing autosetting.
 * Consider downgrading BIOS to the most stable. ASUS and ASRock have been known to push very beta BIOSs that have shown to be very unstable.
 * Some motherboards' BIOS have an option to disable OPCache. This has been observed to limit or stop segfaults albeit with a 5-7% performance cost.
 * Some users have reported that disabling ASLR resolves the segfault issues. This can be done at runtime by issuing  and to make it permanent:

Related forum topics: 1 and 2. And a Phoronix forum topic.

Ryzen users can also fill Gentoo and Ryzen config and stability questionnaire to help out collecting data. See also the datasheet generated from above questionnaire.

Random reboots with mce events
If your system runs 24x7 and you encounter random, spontaneous reboots with MCE hardware errors being logged on startup, consider disabling C-States in the BIOS. An example MCE event looks like this: Oct 31 11:46:23 fire kernel: [   0.677235] [Hardware Error]: System Fatal error. Oct 31 11:46:23 fire kernel: [   0.677439] [Hardware Error]: CPU:10 (17:1:1) MC5_STATUS[-|UE|MiscV|PCC|AddrV|-|-|SyndV|TCC]: 0xbea0000000000108 Oct 31 11:46:23 fire kernel: [   0.677798] [Hardware Error]: Error Addr: 0x0001ffff810796c0 Oct 31 11:46:23 fire kernel: [   0.678003] [Hardware Error]: IPID: 0x000500b000000000, Syndrome: 0x000000004d000000 Oct 31 11:46:23 fire kernel: [   0.678356] [Hardware Error]: Execution Unit Extended Error Code: 0 Oct 31 11:46:23 fire kernel: [   0.678562] [Hardware Error]: Execution Unit Error: Watchdog timeout error. Oct 31 11:46:23 fire kernel: [   0.678562] [Hardware Error]: cache level: RESV, tx: GEN, mem-tx: GEN

See also this AMD forum discussion (and many other discussions).

External resources

 * http://www.phoronix.com/scan.php?page=article&item=amd-ryzen-znver1&num=1 - Phoronix compiler optimization benchmarks for Ryzen 7.