Project:RISC-V

RISC-V CPU architecture support in Gentoo.]]

Status
No first class arch support yet. Early adopters can get a toolchain working.

What works
With help of crossdev and a bit of manual '*'/'~*' keywording you can get the following toolchains to work:


 * riscv64-unknown-linux-gnu: linux glibc target to cross-compile your kernel and stage3 userland
 * riscv64-unknown-elf: newlib target (bare metal?)

qemu-riscv can run the binaries just fine:

What needs to be done
Things to happen yet:


 * TODO: Announce RISC-V project.
 * TODO: Prepare entries.
 * TODO: Add minimal  keywords.
 * TODO: Make stage3 autobuilds.
 * TODO: Sort out multilib story.

Documentation

 * TODO: Add a page that describes how to get riscv toolchain. Basically a and a few tweaks around.
 * TODO: Describe arch-specific gotchas (alignment requirements, immediate encodings, PIS crosry).
 * TODO: Add external links to ISA and ABI docs.
 * RISC-V ABIs
 * RISC-V Multilib